Official Gazette Notification Text
Official TranscriptGOVERNMENT OF INDIA MINISTRY OF ELECTRONICS AND INFORMATION TECHNOLOGY LOK SABHA UNSTARRED QUESTION NO. 2962 TO BE ANSWERED ON: 05.08.2026 CHIP DESIGN PROJECTS APPROVED UNDER DLI SCHEME 2962. SHRI MANISH TEWARI: Will the Minister of ELECTRONICS AND INFORMATION TECHNOLOGY be pleased to state: (a) whether any of the 24 chip design projects approved under Designed Linked Incentive (DLI) Scheme have...
GOVERNMENT OF INDIA MINISTRY OF ELECTRONICS AND INFORMATION TECHNOLOGY LOK SABHA UNSTARRED QUESTION NO. 2962
TO BE ANSWERED ON: 05.08.2026 CHIP DESIGN PROJECTS APPROVED UNDER DLI SCHEME
2962. SHRI MANISH TEWARI:
Will the Minister of ELECTRONICS AND INFORMATION TECHNOLOGY be pleased to
state:
(a) whether any of the 24 chip design projects approved under Designed Linked Incentive (DLI) Scheme have progressed to commercial deployment and revenue generation and if so, the details thereof disaggregated by sector and application;
(b) if not, the reasons for none reaching deployment despite programme being operational since the year 2021;
(c) whether the claim of India possessing nearly 20 per cent of global semiconductor design talent has translated into commercially deployed chips and if so, the details of such chips, companies and revenue generated and if not, the reasons for the gap;
(d) whether the 175 chips fabricated by students under the C2S programme have any commercial application and if so, the details thereof and if not, the details of steps planned to bridge the gap between academic fabrication and industry deployment; and
(e) whether the 15 companies that received venture capital support under the DLI Scheme have disclosed milestones achieved and revenue generated and if so, the disaggregated details thereof and if not, the accountability mechanisms in place for such publicly facilitated investments? ANSWER MINISTER OF STATE FOR ELECTRONICS AND INFORMATION TECHNOLOGY (SHRI JITIN PRASADA)
(a) to (e): Guided by the vision of the Hon'ble Prime Minister Shri Narendra Modi to make India a global hub for semiconductor chip design, the Government has undertaken focused policy interventions and sustained investments in semiconductor education, research, and design infrastructure, thereby strengthening the country's semiconductor design ecosystem and talent base.
Towards this end, the Government has accorded high priority to workforce capacity building and indigenous chip design through two complementary initiatives, the Chips to Startup (C2S) Programme and the Design Linked Incentive (DLI) Scheme.
While the C2S Programme focuses on developing industry-ready talent and strengthening academic research capabilities, the DLI Scheme supports startups and MSMEs in chip design area.
Together, these initiatives have helped create a strong semiconductor design talent and vibrant chip design base in the country.
As per industry estimates, India accounts for about 20% of the world's semiconductor design engineers, with more than 1.25 lakh semiconductor design engineers working in the country. Indiaalso hosts about 7% of the world's semiconductor Global Capability Centres (GCCs), reflecting its growing importance in the global semiconductor design ecosystem.
Under the C2S Programme, capacity-building projects have been supported at academic institutions in collaboration with startups, to foster research on industry-oriented problem statements and provide students with hands-on exposure to the end-to-end semiconductor chip design lifecycle. This has resulted in the training of over 68,000 students, and the successful tape- out of 254 chip designs by students including 175 designs at the 180 nm technology node at SCL, Mohali, and 79 designs at overseas foundries.
Complementing these capacity-building efforts, the DLI Scheme has resulted following
outcomes: ● 24 projects from startups/ MSMEs have been approved during the period from mid- 2023 to 2025 for financial support to develop semiconductor chips. ● The approved projects address critical sectors such as video surveillance, drone detection, energy metering, microprocessors, satellite communications, Light Emitting Diode (LED) drivers, broadband, and Internet of Things (IoT) System-on-Chips
(SoCs). ● The beneficiary companies have collectively attracted venture capital (VC) investment amounting to more than four times the financial assistance disbursed under the DLI Scheme, reflecting strong confidence of industry and investors in the technological capabilities and commercial potential of these companies.
● So far, 25 chip designs have been successfully taped out across multiple foundries, including at advanced technology nodes such as 12 nm at TSMC. Some of these designs have subsequently progressed to customer evaluation and qualification stages.
Semiconductor chip design, unlike software product development, involves a highly complex, capital-intensive and multi-stage engineering process that follows a globally established product development lifecycle. Before a semiconductor product reaches commercial deployment, it typically progresses, inter alia, through the following stages over a period that may extend up to five years or more, depending upon the complexity of the chip:
● Architecture definition, RTL design and verification ● Physical design, timing closure, tape-out and first-silicon fabrication ● Post-silicon validation, characterization and subsequent fabrication iterations ● Certification, qualification, benchmarking and user acceptance.
The successful tape-out of 25 chip designs across multiple foundries, including at advanced technology nodes, together with the mobilization of venture capital investment exceeding four times the Government's financial assistance disbursed, demonstrates steady progress of DLI beneficiary companies towards commercialization.
Such progress is consistent with globally accepted semiconductor product development cycles and industry benchmarks for companies undertaking indigenous chip development for the first time.
These achievements stand as a testimony to the effectiveness of the DLI Scheme and the strong technological and commercial potential of the supported companies. *****